1. Field of the Invention
The present invention disclosed herein relates to semiconductor devices and methods of fabricating the same. More particularly, the invention relates to semiconductor devices having a transistor with an extended channel width and methods of fabricating the same.
2. Description of the Related Art
As semiconductor memory devices are becoming smaller and/or more highly-integrated, a channel length and width of transistors included therein are becoming smaller. A line-width of an active region corresponding to the channel width of the transistor is also being reduced.
In general, a memory device for storing information may include a cell array with patterns having minimum line-widths. In a cell array region of the memory device, an active region and a device isolation region may be formed such that they have minimum line-widths corresponding to a gate pattern of a transistor.
However, as line-width(s) of the gate pattern(s) are reduced, a sufficient channel length should be provided in order to suppress and/or prevent short channel effect and leakage current. A structure in which an effective channel length of the transistor is increased by, e.g., etching a portion of the active region to form a recess region has been developed. In such cases, the channel length may be secured without increasing a gate line-width by forming the channel of the transistor in the recess region.
However, in such cases, problems may occur, e.g., the recess region may be filled with a gate insulating layer, and/or it may be difficult to secure an effective channel width because the channel is formed in a portion of the recess region. When the effective channel length is not sufficiently secured, a driving current may be decreased and a gate controllability of the transistor may be lowered, which may negatively impact leakage current and threshold voltage characteristics.
Flash memory devices may employ a method of forming a channel of a selection transistor in a recess region in order to suppress and/or prevent gate-induced drain leakage (GIDL) and punchthrough, and to avoid program/erase errors of an outermost cell transistor of a cell string. However, if minimum line-widths are reduced in order to provide highly-integrated devices, e.g., to about or less than about two times a thickness of a gate insulating layer, the gate insulating layer may completely fill the recess region. Thus, gate controllability of the transistor may be degraded, which may cause the transistor to operate abnormally.